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#define | CV_CPU_CALL_AVX(fn, args) |
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#define | CV_CPU_CALL_AVX2(fn, args) |
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#define | CV_CPU_CALL_AVX2_(fn, args) |
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#define | CV_CPU_CALL_AVX512_SKX(fn, args) |
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#define | CV_CPU_CALL_AVX512_SKX_(fn, args) |
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#define | CV_CPU_CALL_AVX_(fn, args) |
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#define | CV_CPU_CALL_AVX_512F(fn, args) |
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#define | CV_CPU_CALL_AVX_512F_(fn, args) |
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#define | CV_CPU_CALL_BASELINE(fn, args) return (cpu_baseline::fn args) |
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#define | CV_CPU_CALL_FMA3(fn, args) |
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#define | CV_CPU_CALL_FMA3_(fn, args) |
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#define | CV_CPU_CALL_FP16(fn, args) |
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#define | CV_CPU_CALL_FP16_(fn, args) |
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#define | CV_CPU_CALL_NEON(fn, args) |
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#define | CV_CPU_CALL_NEON_(fn, args) |
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#define | CV_CPU_CALL_POPCNT(fn, args) |
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#define | CV_CPU_CALL_POPCNT_(fn, args) |
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#define | CV_CPU_CALL_SSE(fn, args) |
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#define | CV_CPU_CALL_SSE2(fn, args) |
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#define | CV_CPU_CALL_SSE2_(fn, args) |
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#define | CV_CPU_CALL_SSE3(fn, args) |
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#define | CV_CPU_CALL_SSE3_(fn, args) |
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#define | CV_CPU_CALL_SSE4_1(fn, args) |
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#define | CV_CPU_CALL_SSE4_1_(fn, args) |
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#define | CV_CPU_CALL_SSE4_2(fn, args) |
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#define | CV_CPU_CALL_SSE4_2_(fn, args) |
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#define | CV_CPU_CALL_SSE_(fn, args) |
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#define | CV_CPU_CALL_SSSE3(fn, args) |
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#define | CV_CPU_CALL_SSSE3_(fn, args) |
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#define | CV_CPU_CALL_VSX(fn, args) |
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#define | CV_CPU_CALL_VSX_(fn, args) |
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#define | CV_CPU_FORCE_AVX 0 |
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#define | CV_CPU_FORCE_AVX2 0 |
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#define | CV_CPU_FORCE_AVX512_SKX 0 |
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#define | CV_CPU_FORCE_AVX_512F 0 |
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#define | CV_CPU_FORCE_FMA3 0 |
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#define | CV_CPU_FORCE_FP16 0 |
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#define | CV_CPU_FORCE_NEON 0 |
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#define | CV_CPU_FORCE_POPCNT 0 |
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#define | CV_CPU_FORCE_SSE 0 |
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#define | CV_CPU_FORCE_SSE2 0 |
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#define | CV_CPU_FORCE_SSE3 0 |
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#define | CV_CPU_FORCE_SSE4_1 0 |
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#define | CV_CPU_FORCE_SSE4_2 0 |
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#define | CV_CPU_FORCE_SSSE3 0 |
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#define | CV_CPU_FORCE_VSX 0 |
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#define | CV_CPU_HAS_SUPPORT_AVX 0 |
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#define | CV_CPU_HAS_SUPPORT_AVX2 0 |
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#define | CV_CPU_HAS_SUPPORT_AVX512_SKX 0 |
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#define | CV_CPU_HAS_SUPPORT_AVX_512F 0 |
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#define | CV_CPU_HAS_SUPPORT_FMA3 0 |
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#define | CV_CPU_HAS_SUPPORT_FP16 0 |
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#define | CV_CPU_HAS_SUPPORT_NEON 0 |
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#define | CV_CPU_HAS_SUPPORT_POPCNT 0 |
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#define | CV_CPU_HAS_SUPPORT_SSE 0 |
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#define | CV_CPU_HAS_SUPPORT_SSE2 0 |
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#define | CV_CPU_HAS_SUPPORT_SSE3 0 |
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#define | CV_CPU_HAS_SUPPORT_SSE4_1 0 |
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#define | CV_CPU_HAS_SUPPORT_SSE4_2 0 |
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#define | CV_CPU_HAS_SUPPORT_SSSE3 0 |
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#define | CV_CPU_HAS_SUPPORT_VSX 0 |
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#define | CV_TRY_AVX 0 |
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#define | CV_TRY_AVX2 0 |
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#define | CV_TRY_AVX512_SKX 0 |
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#define | CV_TRY_AVX_512F 0 |
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#define | CV_TRY_FMA3 0 |
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#define | CV_TRY_FP16 0 |
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#define | CV_TRY_NEON 0 |
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#define | CV_TRY_POPCNT 0 |
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#define | CV_TRY_SSE 0 |
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#define | CV_TRY_SSE2 0 |
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#define | CV_TRY_SSE3 0 |
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#define | CV_TRY_SSE4_1 0 |
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#define | CV_TRY_SSE4_2 0 |
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#define | CV_TRY_SSSE3 0 |
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#define | CV_TRY_VSX 0 |
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